View MDT2005JG_4219352.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MDT2005(JG)
1. General Description
This EPROM-Based 8-bit micro-controller uses a fully static CMOS design technology combines higher speeds and smaller size with the low power and high noise immunity of CMOS. On chip memory system includes 0.5 K(for MDT2005) bytes of ROM, and 32 bytes of static RAM. Power-on Reset (POR) only available while PED is Disable Power edge-detector Reset (PED) Sleep Mode for power saving 8-bit real time clock/counter(RTCC) with 8-bit programmable prescaler 4 types of oscillator can be selected by programming option: RC Low cost RC oscillator LFXT Low frequency crystal oscillator XTAL Standard crystal oscillator HFXT High frequency crystal oscillator 4 oscillator start-up time can be selected by programming option: 150 s, 20 ms, 40 ms, 80 ms On-chip RC oscillator based Watchdog Timer(WDT) can be operated freely 12 I/O pins with their own independent direction control
2. Features
The followings are some of the features on the hardware and software : Fully CMOS static design 8-bit data bus On chip ROM size : 512 words for MDT2005 Internal RAM size : 32 bytes (25 general purpose registers, 7 special registers) 36 single word instructions 14-bit instructions 2-level stacks Operating voltage : 2.3V ~ 6.0 V Operating frequency : 0 ~ 20 MHz The most fast execution time is 200 ns under 20 MHz in all single cycle instructions except the branch instruction Addressing modes include direct, indirect and relative addressing modes
3. Applications
The application areas of this MDT2005 range from appliance motor control and high speed automotive to low power remote transmitters/receivers, pointing devices, and telecommunications processors, such as Remote controller, small instruments, chargers, toy, automobile and PC peripheral ... etc.
This specification are subject to be changed without notice. Any latest information http;//www.mdtic.com.tw
please preview
P. 1
2006/4
VER1.1
MDT2005(JG)
4. Pin Assignment
DIP / SOP 18 17 16 15 14 13 12 11 10
SSOP
PA1 PA0 OSC1 OSC2 Vdd PB7 PB6 PB5 PB4 PA2 PA3 RTCC /MCLR VSS VSS PB0 PB1 PB2 PB3 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PA1 PA0 OSC1 OSC2 VDD VDD PB7 PB6 PB5 PB4
PA2 PA3 RTCC /MCLR Vss PB0 PB1 PB2 PB3
1 2 3 4 5 6 7 8 9
5. Pin Function Description
Pin Name PA0~PA3 PB0~PB7 RTCC /MCLR OSC1 OSC2 Vdd Vss I/O I/O I/O I I I O Function Description Port A, TTL input level Port B, TTL input level Real Time Clock/Counter, Schmitt Trigger input levels Master Clear, Schmitt Trigger input levels Oscillator Input Oscillator Output Power supply Ground
This specification are subject to be changed without notice. Any latest information http;//www.mdtic.com.tw
please preview
P. 2
2006/4
VER1.1
MDT2005(JG)
6. Memory Map
(A) Register Map Address 00 01 02 03 04 05 06 07~1F Description Indirect Addressing Register RTCC PC STATUS MSR Port A Port B Internal RAM, General Purpose Register
(1) IAR ( Indirect Address Register) : R0 (2) RTCC (Real Time Counter/Counter Register) : R1 (3) PC (Program Counter) : R2
Write PC, CALL --- always 0 LJUMP, JUMP, LCALL --- from instruction word RTWI, RET --- from STACK
A9
A8
A7~A0
Write PC, JUMP, CALL --- always 0 (ROM 0.5K) LJUMP, LCALL --- from instruction word RTWI, RET --- from STACK
Write PC --- from ALU LJUMP, JUMP, LCALL, CALL --- from instruction word RTWI, RET --- from STACK
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 2
2006/4
VER1.1
MDT2005(JG)
(4) STATUS (Status register) : R3 Bit 0 1 2 3 4 5-7 Symbol C HC Z PF TF Carry bit Half Carry bit Zero bit Power loss Flag bit Time overflow Flag bit General purpose bit Function
(5) MSR (Memory Select Register) : R4 (6) PORT A : R5 PA3~PA0, I/O Register (7) PORT B : R6 PB7~PB0, I/O Register (8) TMR (Time Mode Register) Bit Symbol Prescaler Value Function RTCC rate WDT rate 000 1:2 1:1 001 1:4 1:2 010 1:8 1:4 011 1 : 16 1:8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 Prescaler assignment bit : 0 RTCC 1 Watchdog Timer RTCC signal Edge : 0 Increment on low-to-high transition on RTCC pin 1 Increment on high-to-low transition on RTCC pin RTCC signal set : 0 Internal instruction cycle clock 1 Transition on RTCC pin
2
0
PS2
0
3
PSC
4
TCE
5
TCS
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 3
2006/4
VER1.1
MDT2005(JG)
(9) CPIO A, CPIO B (Control Port I/O Mode Register) The CPIO register is "write-only" "0", I/O pin in output mode; "1", I/O pin in input mode. (10) EPROM Option by writer programming : Oscillator Type RC Oscillator Oscillator Start-up Time 150 s,20ms,40ms,80ms 20 ms,40ms,80ms 20ms,40 ms,80ms 40 ms,80 ms
HFXT Oscillator XTAL Oscillator LFXT Oscillator
Watchdog Timer control Watchdog timer disable all the time Watchdog timer enable all the time
Power Edge Detect PED Disable PED Enable
Security bit Security weak Disable Security Disable Security Enable
The default EPROM security is weak disable. Once the IC was set in enable or disable, it's forbidden to set in disable or enable again. (B) Program Memory Address 000-1FF 1FF Description Program memory for MDT2005 The starting address of the power on, external reset or WDT for MDT2005
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 4
2006/4
VER1.1
MDT2005(JG)
7. Reset Condition for all Registers
Register CPIO A CPIO B TMR IAR RTCC PC STATUS MSR PORT A PORT B 00h 01h 02h 03h 04h 05h 06h xxxx xxxx 1111 1111 0001 1xxx 111x xxxx - - - - xxxx xxxx xxxx uuuu uuuu 1111 1111 000# #uuu 111u uuuu - - - - uuuu uuuu uuuu Address Power-On Reset 1111 1111 1111 1111 --11 1111 /MCLR or WDT Reset 1111 1111 1111 1111 --11 1111
Note : u unchanged, x unknown, - unimplemented, read as "0" # value depends on the condition of the following table Condition /MCLR reset (not during SLEEP) /MCLR reset during SLEEP WDT reset (not during SLEEP) WDT reset during SLEEP Status: bit 4 u 1 0 0 Status: bit 3 u 0 1 0
8. Instruction Set
Instruction Code 010000 00000000 010000 00000001 010000 00000010 010000 00000011 010000 00000100 010000 00000rrr 010001 1rrrrrrr 011000 trrrrrrr 111010 iiiiiiii Mnemonic Operands NOP CLRWT SLEEP TMODE RET CPIO R STWR R LDR R, t LDWI I Function No operation Clear Watchdog timer Sleep mode Load W to TMODE register Return Control I/O port register Store W to register Load register Load immediate to W Operating None 0 0 W W W R I WT TMODE PC r CPIO R t W TF, PF None None None None Z None WT, stop OSC TF, PF Status
Stack
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 5
2006/4
VER1.1
MDT2005(JG)
Instruction Code 010111 trrrrrrr 011001 trrrrrrr 011010 trrrrrrr 011011 trrrrrrr 011100 trrrrrrr 011101 trrrrrrr 011110 trrrrrrr 010010 trrrrrrr 110100 iiiiiiii 010011 trrrrrrr 110101 iiiiiiii 010100 trrrrrrr 110110 iiiiiiii 011111 trrrrrrr 010110 trrrrrrr 010101 trrrrrrr 010000 1xxxxxxx 010001 0rrrrrrr 0000bb brrrrrrr 0010bb brrrrrrr 0001bb brrrrrrr 0011bb brrrrrrr 1000nn nnnnnnnn 1010nn nnnnnnnn 110000 nnnnnnnn 110001 iiiiiiii 11001n nnnnnnnn Mnemonic Operands SWAPR R, t INCR R, t INCRSZ R, t ADDWR R, t SUBWR R, t DECR R, t ANDWR R, t ANDWI IORWI XORWI RRR RLR CLRW CLRR BCR BSR R R, b R, b i i R, t R, t i IORWR R, t XORWR R, t COMR R, t Function Swap halves register Increment register Increment register, skip if zero Add W and register Subtract W from register Decrement register AND W and register AND W and immediate Inclu. OR W and register Inclu. OR W and immediate Exclu. OR W and register Exclu. OR W and immediate Complement register Rotate right register Rotate left register Clear working register Clear register Bit clear Bit set Bit Test, skip if clear Bit Test, skip if set Long CALL subroutine Long JUMP to address Call subroutine Return, place immediate to W JUMP to address Operating [R(0~3) R(4~7)] t R+1 R+1 W+R t t t Status None Z None C, HC, Z C, HC, Z Z None t W t W t W Z Z Z Z Z Z Z C C Z Z None None None None None None None W None None
R Wt (R+/W+1 t) R R i R i 1 1 W W W W t t
DECRSZ R, t Decrement register, skip if zero R
RW iW /R t
R(n) R(n-1), C R(7), R(0) C R(n) r(n+1),C R(0), R(7) C 0 0 0 1 W R R(b) R(b)
BTSC R, b BTSS R, b LCALL n LJUMP n CALL RTWI JUMP n i n
Skip if R(b)=0 Skip if R(b)=1 n PC, PC+1 Stack n PC n PC, PC+1 Stack Stack n PC PC, i
Note : W WT TMODE CPIO : : : : Working register Watchdog timer TMODE mode register Control I/O port register b t : : 0 1 Bit position Target : Working register : General register
please preview http;//www.mdtic.com.tw
This specification are subject to be changed without notice. Any latest information
P. 6
2006/4
VER1.1
MDT2005(JG)
TF PF PC OSC Inclu. Exclu. AND : : : : : : : Timer overflow flag Power loss flag Program Counter Oscillator Inclusive ` ' Exclusive ` ' Logic AND ` ' R C HC Z / x i n : : : : : : : : General register address Carry flag Half carry Zero flag Complement Don't care Immediate data ( 8 bits ) Immediate address
9. Electrical Characteristics
(A) Operating Voltage & Frequency Vdd 2.3V ~ 6.0 V
Frequency 0 Hz ~ 20 MHz (B) Input Voltage @ Vdd 5.0 V, Temperature Port Vil Vih PA, PB RTCC, /MCLR PA, PB 25 Min. Vss Vss 2.0 V Max. 1.0 V 1.0V Vdd Vdd
RTCC, /MCLR 3.2 V Threshold Voltage : Port A, Port B Vth 1.5V RTCC, /MCLR Vil 1.2 V, Vih 2.9 V (C) Output Voltage @ Vdd 5.0 V, Temperature PA, PB Port Ioh Iol Ioh Iol 20.0 mA 20.0 mA 5.0 mA 5.0 mA Voh 3.7 V Vol Vol 0.5 V Voh 4.7 V 0.2 V 25
(Schmitt Trigger)
, the typical value as followings :
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 7
2006/4
VER1.1
MDT2005(JG)
(D) Leakage Current @ Vdd 5.0 V, Temperature Iil Iih 25 , the typical value as followings :
0.1A (Max.) 0.1A (Max.)
(E) Sleep Current @WDT Disable, Temperature Vdd 2.3 V Vdd 3.0 V Vdd 4.0 V Vdd 5.0 V Vdd 6.0V
25
, the typical value as followings :
Idd 0.1 A Idd 0.1 A Idd 0.1.A Idd 0.1 A Idd 0.1 A
@WDT
Enable, Temperature
25
, the typical value as followings :
Vdd 2.3 V Vdd 3.0 V Vdd 4.0 V Vdd 5.0 V Vdd 6.0 V (F) Operating Current Temperature 25 (i) OSC Type
Idd 1.0 A Idd 3.0 A Idd 8.0 A Idd 15.0 A Idd 25.0 A
, the typical value as followings : WDT Enable;
RC (OSC1&OSC2 Internal Cap about 10P);
The IC may not oscillate properly if the resistance of rext less than 4.7K. The minimum resistance of rext must be more than 4.7K. @ Vdd 5.0 V Cext. (F) Rext. (Ohm) 4.7 K 10.0 K 0P 47.0 K 100.0 K 300.0 K 470.0 K Frequency (Hz) 11 M 5.2 M 1.37 M 650 K 220 K 140 K Current (A) 1.1 mA 650 A 250 A 175 A 135 A 130 A
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 8
2006/4
VER1.1
MDT2005(JG)
Cext. (F) Rext. (Ohm) 4.7 K 10.0 K 3P 47.0 K 100.0 K 300.0 K 470.0 K 4.7 K 10.0 K 20P 47.0 K 100.0 K 300.0 K 470.0 K 4.7 K 10.0 K 100P 47.0 K 100.0 K 300.0 K 470.0 K 4.7 K 10.0 K 300P 47.0 K 100.0 K 300.0 K 470.0 K Frequency (Hz) 9.4 M 4.45 M 1.1 M 540 K 180 K 115 K 5.5 M 2.5 M 615 K 300 K 100 K 63.5 K 2.0 M 910 K 222 K 105 K 36 K 22 K 870 K 380 K 93 K 44 K 15 K 9.4 K Current (A) 1.1 mA 550 A 230 A 165 A 135 A 125 A 660 A 365 A 185 A 155 A 135 A 125 A 315 A 200 A 135 A 125 A 120 A 115 A 195 A 150 A 120 A 115 A 110 A 108 A 1M Sleep 0.1 A 0.1 A 0.1 A 0.1 A 0.1 A
(ii) OSC Type LF (OSC1&OSC2 Internal cap. ); WDT Disable ;PED=Enable Voltage/Frequency 2.3 V 3.0 V 4.0 V 5.0 V 6.0 V 32 K 455 K (Ext C=50P) (Ext C=50P) 10 A 18 A 35 A 60 A 120 A 40 A 70 A 110 A 180 A
21 A @2.5V 35 A 50 A 85 A 130 A 250 A
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 9
2006/4
VER1.1
MDT2005(JG)
(iii) OSC Type XT (OSC1&OSC2 Internal cap. about 10P); Voltage/Frequency 2.1 V 3.0 V 4.0 V 5.0 V 6.0 V (iv) OSC Type 1M 35 A 80 A 155 A 260 A 410 A 4M 105 A 185 A 305 A 450 A 700 A WDT Enable Sleep 1.0 A 3 A 8 A 15 A 25 A Enable Sleep 1.0 A 3 A 8 A 15 A 25 A
10 M 240 A 380 A 600 A 880 A 1.2 mA WDT
HF (OSC1&OSC2 Internal cap. about 10P); 4M 110 A 210 A 350 A 530 A 850 A 10 M 410 A 640 A 950 A 1.3 mA 20 M
Voltage/Frequency 2.1 V 3.0 V 4.0 V 5.0 V 6.0 V
240 A @2.5V 550A 730 A 1.1 mA 1.6 mA 2.3 mA
(G) Power Edge-detector Reset Voltage (Not in Sleep Mode), @ Vdd 5.0 V(PED Enable) Vpr 1.6~1.8 V Vpr Vdd (Power Supply)
PS.IF PED_Enable then Internal Power_on_reset will be off
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 10
2006/4
VER1.1
MDT2005(JG)
(H) The basic WDT time-out cycle time @ Vdd=5.0v ,Temperature Voltage (V) 2.3 3.0 4.0 5.0 6.0 25 , the typical value as followings :
Basic WDT time-out cycle time (ms) 24.0 22.0 20.5 18.5 18.0
(I) MCLRB Filter @ Vdd=5.0v Wm 1.2us Wm : Filter pulse width (low) in /MCLR pin.
10. Port A and Port B Equivalent Circuit
Working Register
D QB
Data I/P
I/O Control
CK
I/O Control Latch
Q
Port I/O Pin
D
Write
CK
Data O/P Latch
Q
Data Bus
QB D
Read
Data I/P Latch
CK
Input Resistor TTL Input Level
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 11
2006/4
VER1.1
MDT2005(JG)
11. MCLRB and RTCC Input Equivalent Circuit
R
1K
RTCC Schmitt Trigger
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 12
2006/4
VER1.1
MDT2005(JG)
12. Block Diagram
9 or10 bits 9 or 10 bits 14 bits
D0~D7
Data 8-bit
RTCC
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 13
2006/4
VER1.1
MDT2005(JG)
13. External Capacitor Selection For Crystal Oscillator
@ Vdd 3.0V~5.0 V Osc. Type Resonator Freq. 20 MHz HF 10 MHz 4 MHz 10 MHz XT 4 MHz 1 MHz 1 MHz LF 455 K 32 K C1 0 pF ~10 pF 0 pF ~50 pF 0 pF ~30 pF 0 pF ~30 pF 0 pF ~50 pF 0 pF ~30 pF 5 pF ~10 pF 10 pF ~50 pF 10 pF ~30 pF C2 0 pF ~20 pF 0 pF ~100 pF 0 pF ~100 pF 0 pF ~50 pF 0 pF ~100 pF 0 pF ~50 pF 5 pF ~10 pF 10 pF ~50 pF 20 pF ~50 pF
To increase the stability of oscillator and the ability of anti-noise, the above values of the external capacitor range can be recommended for reference, but the higher capacitance also increases the start-up time. This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 14
2006/4
VER1.1

▲Up To Search▲

Price & Availability of MDT2005JG

	To Download MDT2005JG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .